1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems having multiple digital signal processor subsystems exchanging data by means of a high level data link controller. The high level data link controller processes a plurality of signal groups from a digital signal processor subsystem and transmits the signal groups as a signal packet. The high level data link controller receives a signal packet and applies reformatted signal groups to the digital signal processor subsystem. The present invention relates to the flow of signal groups from a high level data link controller to a peripheral direct memory access unit.
2. Background of the Invention
As the applications to which the digital signal processor has been applied have increased in magnitude and complexity, the need greater computational power has increased. One response to the requirement of additional computational power has been to provide a plurality of digital signal processor subsystems on a chip. The requirement for additional computational power has also resulted in an increased need for the exchange of signal groups among the plurality of processors and with external components. Several ports have been developed to provide for this signal group exchange. For example, a serial port can be provided that can participate in the exchange of signal groups with other digital signal processors and a host processor. Similarly, a port can be provided that can provide signal group exchange with peripheral units. And a high level data link controller port can be been provided that permits the exchange of packets of signals used in communication applications.
Referring to FIG. 1, a digital signal processor system 1 having a plurality of digital signal processor subsystems 10(1) through 10(N), according to the prior art, is shown. Each digital signal processor subsystem 10(1) includes a central processing unit (digital signal processor core) 101 and a memory unit 103. The central processing unit 101 processes signal groups stored in the memory unit 103 and exchanges signals therewith. The direct memory access unit 105 is coupled to the memory unit 103 and permits the exchange of signals between the memory unit 103 and external components without impact upon the performance of the central processing unit 101. The central processing unit 101 is also coupled to a host port interface unit 115. The host port interface unit 115 enables the central processing unit 101 to communicate with the host processing unit (not shown). Coupled to the direct memory access unit 105 typically are a multi-channel buffered serial port 107, a peripheral component interface unit 109 and high level data link controller unit 111. The multi-channel buffered serial unit 107 exchanges signal groups in a serial format with the host computer unit and off-chip devices. The peripheral component interconnect unit 109 permits the exchange of signals with off-chip peripheral devices. The high level data link controller 111 permits the exchange of packets of signal groups, typically used in communication protocols, with off chip components.
As will be clear from FIG. 1, the subsystems 10(1) through 10(N) operate independently. Thus, a complete set of interface units to exchange signal groups with off chip components must be supplied for each subsystem 10(1) through 10(N) to insure that the operation of each subsystem 10(1) through 10(N) will not be limited. However, the result of provision of a complete set of interface units with each subsystem is an inefficient use of the semiconductor material and components that are not efficiently used. The signal packets applied to the high level data link controller must be directed rapidly and efficiently to the correct central processing unit.
A need has been felt for apparatus and an associated method having the feature of reducing component redundancy resulting from the duplication of components in a multiprocessor component. The apparatus and associated method would have the more particular feature of reducing the number of interface components on the chip. It would be yet another feature of the apparatus and associated method that the subsystems on the chip would share interface components. It would be a still further feature of the apparatus and associated method that a single high level data link controller can receive and process signal packets and forward the processed packet to a central processing unit designated by the packet address. It would be yet a further feature of the apparatus and associated method to forward processed signals from the packet to a buffer memory in the channel of the addressed central processing unit. It would be still further feature of the apparatus and associated method to be able to direct a received packet to central processing unit different from the central processing unit indicated by the address included in the received signal packet.
The aforementioned and other features are accomplished, according to the present invention, by providing a data processing subsystem having a plurality of digital signal processing components, a shared memory subsystem, and a global direct memory access subsystem on a chip. Each digital signal processing subsystem includes a central processing unit and a memory unit. The global direct memory access subsystem includes a peripheral direct memory access unit and high level data link controller. The peripheral direct memory access unit includes a channel associated with each digital signal processing components. Each channel includes a buffer memory for temporary storage of the processed received signal packet prior to forwarding the processed signal packet to the digital signal processing component associated with the channel. The high level data link controller includes a first in-first out memory unit for storage of processed signal groups prior to transfer to the buffer memory unit in the peripheral direct access unit. The high level data link memory unit includes a channel block unit that receives the address signal group of the received packet and, based on the address signal group, generates and INTERRUPT signal that identifies channel/digital signal processing component to which the received packet is directed. This INTERRUPT signal is applied to a switch unit in the peripheral direct memory access unit. In response to the INTERRUPT signal, the switch directs the processed signal groups in the first in-first out storage unit to the channel buffer storage unit associated with the digital signal processing component to which the received signal packet is directed. The channel block unit can, in response to predetermined signal groups, change the digital signal processing component to a different component from the component specified in the address portion of the received packet.